CLK
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(Event 1)
Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks)
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ISSUE
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(Event 2)
Instructions issued but not retired
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RET
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(Event 3)
Instructions retired
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NISSUE
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(Event 4)
Cycles no issue
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SISSUE
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(Event 5)
Cycles single issue
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DISSUE
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(Event 6)
Cycles dual issue
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IFI
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(Event 7)
Cycle ifetch issued (but not necessarily commit to pp_mem)
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BR
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(Event 8)
Branches retired
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BRMIS
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(Event 9)
Branch mispredicts
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J
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(Event 10)
Jumps retired
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JMIS
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(Event 11)
Jumps mispredicted
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REPLAY
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(Event 12)
Mem Replays
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IUNA
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(Event 13)
Cycles idle due to unaligned_replays
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TRAP
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(Event 14)
trap_6a signal
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UULOAD
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(Event 16)
Unexpected unaligned loads (REPUN=1)
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UUSTORE
|
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(Event 17)
Unexpected unaligned store (REPUN=1)
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ULOAD
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(Event 18)
Unaligned loads (REPUN=1 or USEUN=1)
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USTORE
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(Event 19)
Unaligned store (REPUN=1 or USEUN=1)
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EC
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(Event 20)
Exec clocks(must set CvmCtl[DISCE] for accurate timing)
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MC
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(Event 21)
Mul clocks(must set CvmCtl[DISCE] for accurate timing)
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CC
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(Event 22)
Crypto clocks(must set CvmCtl[DISCE] for accurate timing)
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CSRC
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(Event 23)
Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing)
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CFETCH
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(Event 24)
Icache committed fetches (demand+prefetch)
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CPREF
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(Event 25)
Icache committed prefetches
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ICA
|
(Event 26)
Icache aliases
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II
|
(Event 27)
Icache invalidates
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IP
|
(Event 28)
Icache parity error
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CIMISS
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(Event 29)
Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing)
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WBUF
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(Event 32)
Number of write buffer entries created
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WDAT
|
(Event 33)
Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts)
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WBUFLD
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(Event 34)
Number of write buffer entries forced out by loads
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WBUFFL
|
(Event 35)
Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
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WBUFTR
|
(Event 36)
Number of stores that found no available write buffer entries
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BADD
|
(Event 37)
Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
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BADDL2
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(Event 38)
Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts)
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BFILL
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(Event 39)
Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
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DDIDS
|
(Event 40)
Number of Dstream DIDs created
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IDIDS
|
(Event 41)
Number of Istream DIDs created
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DIDNA
|
(Event 42)
Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
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LDS
|
(Event 43)
Number of load issues
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LMLDS
|
(Event 44)
Number of local memory load
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IOLDS
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(Event 45)
Number of I/O load issues
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DMLDS
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(Event 46)
Number of loads that were not prefetches and missed in the cache
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STS
|
(Event 48)
Number of store issues
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LMSTS
|
(Event 49)
Number of local memory store issues
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IOSTS
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(Event 50)
Number of I/O store issues
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IOBDMA
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(Event 51)
Number of IOBDMAs
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DTLB
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(Event 53)
Number of dstream TLB refill, invalid, or modified exceptions
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DTLBAD
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(Event 54)
Number of dstream TLB address errors
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ITLB
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(Event 55)
Number of istream TLB refill, invalid, or address error exceptions
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SYNC
|
(Event 56)
Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
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SYNCIOB
|
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(Event 57)
Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
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SYNCW
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(Event 58)
Number of SYNCWs
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ERETMIS
|
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(Event 64)
D/eret mispredicts (CN63XX specific)
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LIKMIS
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(Event 65)
Branch likely mispredicts (CN63XX specific)
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HAZTR
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(Event 66)
Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific)
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