Manual Pages  — AS

as – Using as (machine specific)

Using as Overview Structure of this Manual The GNU Assembler Object File Formats Command Line Input Files Output (Object) File Error and Warning Messages Command-Line Options Enable Listings: [-a[cdhlns]] [--alternate] [-D] Work Faster: [-f] .include Search Path: [-I path] Difference Tables: [-K] Include Local Symbols: [-L] Configuring listing output: [--listing] Assemble in MRI Compatibility Mode: [-M] Dependency Tracking: [--MD] Name the Object File: [-o] Join Data and Text Sections: [-R] Display Assembly Statistics: [--statistics] Compatible Output: [--traditional-format] Announce Version: [-v] Control Warnings: [-W, [--warn, [--no-warn, [--fatal-warnings]]]] Generate Object File in Spite of Errors: [-Z] Syntax Preprocessing Whitespace Comments Symbols Statements Constants Sections and Relocation Background Linker Sections Assembler Internal Sections Sub-Sections bss Section Symbols Labels Giving Symbols Other Values Symbol Names The Special Dot Symbol Symbol Attributes Expressions Empty Expressions Integer Expressions Assembler Directives .abort .align abs-expr, abs-expr, abs-expr .ascii Va string ... .asciz Va string ... .balign[wl] abs-expr, abs-expr, abs-expr .byte expressions .comm symbol, length .cfi_startproc [simple] .cfi_endproc .cfi_personality encoding [, exp] .cfi_lsda encoding [, exp] .cfi_def_cfa register, offset .cfi_def_cfa_register register .cfi_def_cfa_offset offset .cfi_adjust_cfa_offset offset .cfi_offset register, offset .cfi_rel_offset register, offset .cfi_register register1, register2 .cfi_restore register .cfi_undefined register .cfi_same_value register .cfi_remember_state, .cfi_return_column register .cfi_signal_frame .cfi_window_save .cfi_escape expression[, ...] .file fileno filename .loc fileno lineno[ column][ options] .loc_mark_blocks enable .data subsection .double flonums .eject .else .elseif .end .endfunc .endif .equ symbol, expression .equiv symbol, expression .eqv symbol, expression .err .error Va string .exitm .extern .fail expression .file string .fill repeat, size, value .float flonums .func name[, label] .global symbol,.globl symbol .hidden names .hword expressions .ident .if absolute expression .incbin Va file [, skip[, count]] .include Va file .int expressions .internal names .irp symbol, values... .irpc symbol, values... .lcomm symbol, length .lflags .line line-number .linkonce[ type] .ln line-number .mri val .list .long expressions .macro .altmacro .noaltmacro .nolist .octa biGNUms .org new-lc, fill .p2align[wl] abs-expr, abs-expr, abs-expr .previous .popsection .print string .protected names .psize lines, columns .purgem name .pushsection name, subsection .quad biGNUms .reloc offset, reloc_name[, expression] .rept count .sbttl Va subheading .section name .set symbol, expression .short expressions .single flonums .size .sleb128 expressions .skip size, fill .space size, fill .stabd, .stabn, .stabs .string Va str .struct expression .subsection name .symver .text subsection .title Va heading .type .uleb128 expressions .version Va string .vtable_entry table, offset .vtable_inherit child, parent .warning Va string .weak names .weakref alias, target .word expressions Deprecated Directives ARM Dependent Features Options Syntax Floating Point ARM Machine Directives Opcodes Mapping Symbols 80386 Dependent Features Options AT&T Syntax versus Intel Syntax Instruction Naming Register Naming Instruction Prefixes Memory References Handling of Jump Instructions Floating Point Intel's MMX and AMD's 3DNow! SIMD Operations Writing 16-bit Code AT&T Syntax bugs Specifying CPU Architecture Notes IA-64 Dependent Features Options Syntax Opcodes MIPS Dependent Features Assembler options MIPS ECOFF object code Directives for debugging information Directives to override the size of symbols Directives to override the ISA level Directives for extending MIPS 16 bit instructions Directive to mark data as an instruction Directives to save and restore options Directives to control generation of MIPS ASE instructions PowerPC Dependent Features Options PowerPC Assembler Directives SPARC Dependent Features Options Enforcing aligned data Floating Point Sparc Machine Directives Reporting Bugs Have You Found a Bug? How to Report Bugs Acknowledgements GNU Free Documentation License ADDENDUM: How to use this License for your documents AS Index

This file is a user guide to the GNU assembler as version "2.17.50 [FreeBSD] 2007-07-03". This version of the file describes as configured to generate code for machine specific architectures.

This document is distributed under the terms of the GNU Free Documentation License. A copy of the license is included in the section entitled “GNU Free Documentation License”.

Here is a brief summary of how to invoke as. For details, see Invoking,,Command-Line Options.

as [-a[cdhlns][=file]] [--alternate] [-D]
 [--defsym sym=val] [-f] [-g] [--gstabs]
 [--gstabs+] [--gdwarf-2] [--help] [-I dir] [-J]
 [-K] [-L] [--listing-lhs-width=NUM]
 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
 [--listing-cont-lines=NUM] [--keep-locals] [-o
 objfile] [-R] [--reduce-memory-overheads] [--statistics]
 [-v] [-version] [--version] [-W] [--warn]
 [--fatal-warnings] [-w] [-x] [-Z] [@FILE]
 [--target-help] [target-options]
 [--|files ...]

Target ARM options:
   [-mcpu=processor[+extension...]]
   [-march=architecture[+extension...]]
   [-mfpu=floating-point-format]
   [-mfloat-abi=abi]
   [-meabi=ver]
   [-mthumb]
   [-EB|-EL]
   [-mapcs-32|-mapcs-26|-mapcs-float|
    -mapcs-reentrant]
   [-mthumb-interwork] [-k]


Target i386 options:
   [--32|--64] [-n]
   [-march=CPU] [-mtune=CPU]


Target IA-64 options:
   [-mconstant-gp|-mauto-pic]
   [-milp32|-milp64|-mlp64|-mp64]
   [-mle|mbe]
   [-mtune=itanium1|-mtune=itanium2]
   [-munwind-check=warning|-munwind-check=error]
   [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
   [-x|-xexplicit] [-xauto] [-xdebug]


Target MIPS options:
   [-nocpp] [-EL] [-EB] [-O[optimization level]]
   [-g[debug level]] [-G num] [-KPIC] [-call_shared]
   [-non_shared] [-xgot [-mvxworks-pic]
   [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
   [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
   [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
   [-mips64] [-mips64r2]
   [-construct-floats] [-no-construct-floats]
   [-trap] [-no-break] [-break] [-no-trap]
   [-mfix7000] [-mno-fix7000]
   [-mips16] [-no-mips16]
   [-msmartmips] [-mno-smartmips]
   [-mips3d] [-no-mips3d]
   [-mdmx] [-no-mdmx]
   [-mdsp] [-mno-dsp]
   [-mdspr2] [-mno-dspr2]
   [-mmt] [-mno-mt]
   [-mdebug] [-no-mdebug]
   [-mpdr] [-mno-pdr]


Target PowerPC options:
   [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|
    -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke|
    -mbooke32|-mbooke64]
   [-mcom|-many|-maltivec] [-memb]
   [-mregnames|-mno-regnames]
   [-mrelocatable|-mrelocatable-lib]
   [-mlittle|-mlittle-endian|-mbig|-mbig-endian]
   [-msolaris|-mno-solaris]


Target SPARC options:
   [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
    -Av8plus|-Av8plusa|-Av9|-Av9a]
   [-xarch=v8plus|-xarch=v8plusa] [-bump]
   [-32|-64]

@ file
	Read command-line options from file. The options read are inserted in place of the original @ file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed. Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @ file options; any such options will be processed recursively.
-a[cdhlmns]
	Turn on listings, in any of a variety of ways:
-ac	omit false conditionals
-ad	omit debugging directives
-ah	include high-level source
-al	include assembly
-am	include macro expansions
-an	omit forms processing
-as	include symbols
=file	set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls.

--alternate
	Begin in alternate macro mode.See Section "Altmacro".
-D	Ignored. This option is accepted for script compatibility with calls to other assemblers.
--defsym sym= value
	Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a .set pseudo-op.
-f	“fast”---skip whitespace and comment preprocessing (assume source is compiler output).
-g --gen-debug
	Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2.
--gstabs
	Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
--gstabs+
	Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.
--gdwarf-2
	Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note---this option is only supported by some targets, not all of them.
--help
	Print a summary of the command line options and exit.
--target-help
	Print a summary of all target specific options and exit.
-I dir
	Add directory dir to the search list for .include directives.
-J	Don't warn about signed overflow.
-K	This option is accepted but has no effect on the machine specific family.
-L --keep-locals
	Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems.See Section "Symbol Names".
--listing-lhs-width= number
	Set the maximum width, in words, of the output data column for an assembler listing to number.
--listing-lhs-width2= number
	Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
--listing-rhs-width= number
	Set the maximum width of an input source line, as displayed in a listing, to number bytes.
--listing-cont-lines= number
	Set the maximum number of lines printed in a listing for a single line of input to number + 1.
-o objfile
	Name the object-file output from as objfile.
-R	Fold the data section into the text section. Set the default size of GAS's hash tables to a prime number close to number. Increasing this value can reduce the length of time it takes the assembler to perform its tasks, at the expense of increasing the assembler's memory requirements. Similarly reducing this value can reduce the memory requirements at the expense of speed.
--reduce-memory-overheads
	This option reduces GAS's memory requirements, at the expense of making the assembly processes slower. Currently this switch is a synonym for --hash-size=4051, but in the future it may have other effects as well.
--statistics
	Print the maximum space (in bytes) and total time (in seconds) used by assembly.
--strip-local-absolute
	Remove local absolute symbols from the outgoing symbol table.
-v -version
	Print the as version.
--version
	Print the as version and exit.
-W --no-warn
	Suppress warning messages.
--fatal-warnings
	Treat warnings as errors.
--warn
	Don't suppress warning messages or treat them as errors.
-w	Ignored.
-x	Ignored.
-Z	Generate an object file even after errors.
-- | files ...
	Standard input, or source files to assemble.

The following options are available when as is configured for the ARM processor family.

-mcpu= processor[+ extension...]
	Specify which ARM processor variant is the target.
-march= architecture[+ extension...]
	Specify which ARM architecture variant is used by the target.
-mfpu= floating-point-format
	Select which Floating Point architecture is the target.
-mfloat-abi= abi
	Select which floating point ABI is in use.
-mthumb
	Enable Thumb only instruction decoding.
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
	Select which procedure calling convention is in use.
-EB | -EL
	Select either big-endian (-EB) or little-endian (-EL) output.
-mthumb-interwork
	Specify that the code has been generated with interworking between Thumb and ARM code in mind.
-k	Specify that PIC code has been generated.

The following options are available when as is configured for the SPARC architecture:

-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite -Av8plus | -Av8plusa | -Av9 | -Av9a
	Explicitly select a variant of the SPARC architecture. -Av8plus and -Av8plusa select a 32 bit environment. -Av9 and -Av9a select a 64 bit environment. -Av8plusa and -Av9a enable the SPARC V9 instruction set with UltraSPARC extensions.
-xarch=v8plus | -xarch=v8plusa
	For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
-bump	Warn when the assembler switches to another architecture.

The following options are available when as is configured for a mips processor.

-G num
	This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
-EB	Generate “big endian” format output.
-EL	Generate “little endian” format output.
-mips1 -mips2 -mips3 -mips4 -mips5 -mips32 -mips32r2 -mips64 -mips64r2
	Generate code for a particular mips Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips64, and -mips64r2 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 Release 2 ISA processors, respectively.
-march= CPU
	Generate code for a particular mips cpu.
-mtune= cpu
	Schedule and tune for a particular mips cpu.
-mfix7000 -mno-fix7000
	Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
-mdebug -no-mdebug
	Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
-mpdr -mno-pdr
	Control generation of .pdr sections.
-mgp32 -mfp32
	The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
-mips16 -no-mips16
	Generate code for the MIPS 16 processor. This is equivalent to putting .set mips16 at the start of the assembly file. -no-mips16 turns off this option.
-msmartmips -mno-smartmips
	Enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting .set smartmips at the start of the assembly file. -mno-smartmips turns off this option.
-mips3d -no-mips3d
	Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.
-mdmx -no-mdmx
	Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.
-mdsp -mno-dsp
	Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.
-mdspr2 -mno-dspr2
	Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.
-mmt -mno-mt
	Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option.
--construct-floats --no-construct-floats
	The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default --construct-floats is selected, allowing construction of these floating point constants.
--emulation= name
	This option causes as to emulate as configured for some other target, in all respects, including output format (choosing between ELF and ECOFF only), handling of pseudo-opcodes which may generate debugging information or store symbol table information, and default endianness. The available configuration names are: mipsecoff, mipself, mipslecoff, mipsbecoff, mipslelf, mipsbelf. The first two do not alter the default endianness from that of the primary target for which the assembler was configured; the others change the default to little- or big-endian as indicated by the b or l in the name. Using -EB or -EL will override the endianness selection in any case. This option is currently supported only when the primary target as is configured for is a mips ELF or ECOFF target. Furthermore, the primary target or others specified with --enable-targets=... at configuration time must include support for the other format, if both are to be available. For example, the Irix 5 configuration includes support for both. Eventually, this option will support more configurations, with more fine-grained control over the assembler's behavior, and will be supported for more processors.
-nocpp
	as ignores this option. It is accepted for compatibility with the native tools.
--trap --no-trap --break --no-break
	Control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); --break or --no-trap (also synonyms, and the default) take a break exception.
-n	When this option is used, as will issue a warning every time it generates a nop instruction from a macro.

This manual is intended to describe what you need to know to use GNU as. We cover the syntax expected in source files, including notation for symbols, constants, and expressions; the directives that as understands; and of course how to invoke as.

We also cover special features in the machine specific configuration of as, including assembler directives.

On the other hand, this manual is not intended as an introduction to programming in assembly language---let alone programming in general! In a similar vein, we make no attempt to introduce the machine architecture; we do not describe the instruction set, standard mnemonics, registers or addressing modes that are standard to a particular architecture.

GNU as is really a family of assemblers. This manual describes as, a member of that family which is configured for the machine specific architectures. If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax.

as is primarily intended to assemble the output of the GNU C compiler gcc for use by the linker ld. Nevertheless, we've tried to make as assemble correctly everything that other assemblers for the same machine would assemble.

Unlike older assemblers, as is designed to assemble a source program in one pass of the source file. This has a subtle impact on the .org directive (see Section "Org").

The GNU assembler can be configured to produce several alternative object file formats. For the most part, this does not affect how you write assembly language programs; but directives for debugging symbols are typically different in different file formats.See Section "Symbol Attributes". For the machine specific target, as is configured to produce ELF format object files.

After the program name as, the command line may contain options and file names. Options may appear in any order, and may be before, after, or between file names. The order of file names is significant.

-- (two hyphens) by itself names the standard input file explicitly, as one of the files for as to assemble.

Except for -- any command line argument that begins with a hyphen ( -) is an option. Each option changes the behavior of as. No option changes the way another option works. An option is a - followed by one or more letters; the case of the letter is important. All options are optional.

Some options expect exactly one file name to follow them. The file name may either immediately follow the option's letter (compatible with older assemblers) or it may be the next command argument (GNU standard). These two command lines are equivalent:

as -o my-object-file.o mumble.s
as -omy-object-file.o mumble.s

We use the phrase source program, abbreviated source, to describe the program input to one run of as. The program may be in one or more files; how the source is partitioned into files doesn't change the meaning of the source.

The source program is a concatenation of the text in all the files, in the order specified.

Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.)

You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command line argument (in any position) that has no special meaning is taken to be an input file name.

If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble.

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file.

Filenames and Line-numbers

There are two ways of locating a line in the input file (or files) and either may be used in reporting error messages. One way refers to a line number in a physical file; the other refers to a line number in a “logical” file.See Section "Errors".

Physical files are those files named in the command line given to as.

Logical files are simply names declared explicitly by assembler directives; they bear no relation to physical files. Logical file names help error messages reflect the original source file, when as source is itself synthesized from other files. as understands the # directives emitted by the gcc preprocessor. See also File,, .file amp;.

Every time you run as it produces an output file, which is your assembly language program translated into numbers. This file is the object file. Its default name is a.out. You can give it another name by using the [-o] option. Conventionally, object file names end with .o. The default name is used for historical reasons: older assemblers were capable of assembling self-contained programs directly into a runnable program. (For some formats, this isn't currently possible, but it can be done for the a.out format.)

The object file is meant for input to the linker ld. It contains assembled program code, information to help ld integrate the assembled program into a runnable file, and (optionally) symbolic information for the debugger.

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly.

Warning messages have the format

file_name:NNN:Warning Message Text

(where NNN is a line number). If a logical file name has been given (see Section "File") it is used for the filename, otherwise the name of the current input file is used. If a logical line number was given then it is used to calculate the number printed, otherwise the actual line in the current source file is printed. The message text is intended to be self explanatory (in the grand Unix tradition).

Error messages have the format

file_name:NNN:FATAL:Error Message Text

The file name and line number are derived as for warning messages. The actual message text may be rather less explanatory because many of them aren't supposed to happen.

This chapter describes the machine-independent syntax allowed in a source file. as syntax is similar to what many other assemblers use; it is inspired by the BSD 4.2 assembler.

The as internal preprocessor:

• adjusts and removes extra whitespace. It leaves one space or tab before the keywords on a line, and turns any other whitespace on the line into a single space.

• removes all comments, replacing them with a single space, or an appropriate number of newlines.

• converts character constants into the appropriate numeric values.

It does not do macro processing, include file handling, or anything else you may get from your C compiler's preprocessor. You can do include file processing with the .include directive (see Section "Include"). You can use the GNU C compiler driver to get other “CPP” style preprocessing by giving the input file a .S suffix.See Section "Overall Options".

Excess whitespace, comments, and character constants cannot be used in the portions of the input text that are not preprocessed.

If the first line of an input file is #NO_APP or if you use the -f option, whitespace and comments are not removed from the input file. Within an input file, you can ask for whitespace and comment removal in specific portions of the by putting a line that says #APP before the text that may contain whitespace or comments, and putting a line that says #NO_APP after this text. This feature is mainly intend to support asm statements in compilers whose output is otherwise free of comments and whitespace.

Whitespace is one or more blanks or tabs, in any order. Whitespace is used to separate symbols, and to make programs neater for people to read. Unless within character constants (see Section "Characters"), any whitespace means the same as exactly one space.

There are two ways of rendering comments to as. In both cases the comment is equivalent to one space.

Anything from /* through the next */ is a comment. This means you may not nest these comments.

/*
  The only way to include a newline ('\n') in a comment
  is to use this sort of comment.
*/

/* This sort of comment does not nest. */

Anything from the line comment character to the next newline is considered a comment and is ignored. The line comment character is @ on the ARM; # on the i386 and x86-64; # for Motorola PowerPC; ! on the SPARC; see Machine Dependencies.

To be compatible with past assemblers, lines that begin with # have a special interpretation. Following the # should be an absolute expression (see Section "Expressions"): the logical line number of the next line. Then a string (see Section "Strings") is allowed: if present it is a new logical file name. The rest of the line, if any, should be whitespace.

If the first non-whitespace characters on the line are not numeric, the line is ignored. (Just like a comment.)

                          # This is an ordinary comment.
# 42-6 "new_file_name"    # New logical file name
                          # This is logical line # 36.

This feature is deprecated, and may disappear from future versions of as.

A symbol is one or more characters chosen from the set of all letters (both upper and lower case), digits and the three characters _.$. No symbol may begin with a digit. Case is significant. There is no length limit: all characters are significant. Symbols are delimited by characters not in that set, or by the beginning of a file (since the source program must end with a newline, the end of a file is not a possible symbol delimiter).See Section "Symbols".

A statement ends at a newline character ( \n) or at a semicolon ( ;). The newline or semicolon is considered part of the preceding statement. Newlines and semicolons within character constants are an exception: they do not end statements.

It is an error to end any statement with end-of-file: the last character of any input file should be a newline.

An empty statement is allowed, and may include whitespace. It is ignored.

A statement begins with zero or more labels, optionally followed by a key symbol which determines what kind of statement it is. The key symbol determines the syntax of the rest of the statement. If the symbol begins with a dot . then the statement is an assembler directive: typically valid for any computer. If the symbol begins with a letter the statement is an assembly language instruction: it assembles into a machine language instruction.

A label is a symbol immediately followed by a colon ( :). Whitespace before a label or after a colon is permitted, but you may not have whitespace between a label's symbol and its colon.See Section "Labels".

label:     .directive    followed by something
another_label:           # This is an empty statement.
           instruction   operand_1, operand_2, ...

A constant is a number, written so that its value is known by inspection, without knowing any context. Like this:

amp;.byte  74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
amp;.ascii "Ring the bell\7"                  # A string constant.
amp;.octa  0x123456789abcdef0123456789ABCDEF0 # A biGNUm.
amp;.float 0f-314159265358979323846264338327\
95028841971.693993751E-40                 # - pi, a flonum.

Character Constants

There are two kinds of character constants. A character stands for one character in one byte and its value may be used in numeric expressions. String constants (properly called string literals) are potentially many bytes and their values may not be used in arithmetic expressions.

Strings

A string is written between double-quotes. It may contain double-quotes or null characters. The way to get special characters into a string is to escape these characters: precede them with a backslash \ character. For example \\ represents one backslash: the first \ is an escape which tells as to interpret the second character literally as a backslash (which prevents as from recognizing the second \ as an escape character). The complete list of escapes follows.

\b	Mnemonic for backspace; for ASCII this is octal code 010.
\f	Mnemonic for FormFeed; for ASCII this is octal code 014.
\n	Mnemonic for newline; for ASCII this is octal code 012.
\r	Mnemonic for carriage-Return; for ASCII this is octal code 015.
\t	Mnemonic for horizontal Tab; for ASCII this is octal code 011.
\ digit digit digit
	An octal character code. The numeric code is 3 octal digits. For compatibility with other Unix systems, 8 and 9 are accepted as digits: for example, \008 has the value 010, and \009 the value 011.
\x hex-digits...
	A hex character code. All trailing hex digits are combined. Either upper or lower case x works.
\\	Represents one \ character.
\"	Represents one " character. Needed in strings to represent this character, because an unescaped " would end the string.
\ anything-else
	Any other character when escaped by \ gives a warning, but assembles as if the \ was not present. The idea is that if you used an escape sequence you clearly didn't want the literal interpretation of the following character. However as has no other interpretation, so as knows it is giving you the wrong code and warns you of the fact.

Which characters are escapable, and what those escapes represent, varies widely among assemblers. The current set is what we think the BSD 4.2 assembler recognizes, and is a subset of what most C compilers recognize. If you are in doubt, do not use an escape sequence.

Characters

A single character may be written as a single quote immediately followed by that character. The same escapes apply to characters as to strings. So if you want to write the character backslash, you must write '\\ where the first \ escapes the second \. As you can see, the quote is an acute accent, not a grave accent. A newline (or semicolon ;) immediately following an acute accent is taken as a literal character and does not count as the end of a statement. The value of a character constant in a numeric expression is the machine's byte-wide code for that character. as assumes your character code is ASCII: 'A means 65, 'B means 66, and so on.

Number Constants

as distinguishes three kinds of numbers according to how they are stored in the target machine. Integers are numbers that would fit into an int in the C language. BiGNUms are integers, but they are stored in more than 32 bits. Flonums are floating point numbers, described below.

Integers

A binary integer is 0b or 0B followed by zero or more of the binary digits 01.

An octal integer is 0 followed by zero or more of the octal digits ( 01234567).

A decimal integer starts with a non-zero digit followed by zero or more digits ( 0123456789).

A hexadecimal integer is 0x or 0X followed by one or more hexadecimal digits chosen from 0123456789abcdefABCDEF.

Integers have the usual values. To denote a negative integer, use the prefix operator - discussed under expressions (see Section "Prefix Ops").

BiGNUms

A biGNUm has the same syntax and semantics as an integer except that the number (or its negative) takes more than 32 bits to represent in binary. The distinction is made because in some places integers are permitted while biGNUms are not.

Flonums

A flonum represents a floating point number. The translation is indirect: a decimal floating point number from the text is converted by as to a generic binary floating point number of more than sufficient precision. This generic floating point number is converted to a particular computer's floating point format (or formats) by a portion of as specialized to that computer.

A flonum is written by writing (in order)

• The digit 0.

• A letter, to tell as the rest of the number is a flonum.

• An optional sign: either + or -.

• An optional integer part: zero or more decimal digits.

• An optional fractional part: . followed by zero or more decimal digits.

• An optional exponent, consisting of:
  • An E or e.
  • Optional sign: either + or -.
  • One or more decimal digits.

At least one of the integer part or the fractional part must be present. The floating point number has the usual base-10 value.

as does all processing using integers. Flonums are computed independently of any floating point hardware in the computer running as.

Roughly, a section is a range of addresses, with no gaps; all data “in” those addresses is treated the same for some particular purpose. For example there may be a “read only” section.

The linker ld reads many object files (partial programs) and combines their contents to form a runnable program. When as emits an object file, the partial program is assumed to start at address 0. ld assigns the final addresses for the partial program, so that different partial programs do not overlap. This is actually an oversimplification, but it suffices to explain how as uses sections.

ld moves blocks of bytes of your program to their run-time addresses. These blocks slide to their run-time addresses as rigid units; their length does not change and neither does the order of bytes within them. Such a rigid unit is called a section. Assigning run-time addresses to sections is called relocation. It includes the task of adjusting mentions of object-file addresses so they refer to the proper run-time addresses.

An object file written by as has at least three sections, any of which may be empty. These are named text, data and bss sections.

as can also generate whatever other named sections you specify using the .section directive (see Section "Section"). If you do not use any directives that place output in the .text or .data sections, these sections still exist, but are empty.

Within the object file, the text section starts at address 0, the data section follows, and the bss section follows the data section.

To let ld know which data changes when the sections are relocated, and how to change that data, as also writes to the object file details of the relocation needed. To perform relocation ld must know, each time an address in the object file is mentioned:

• Where in the object file is the beginning of this reference to an address?
• How long (in bytes) is this reference?
• Which section does the address refer to? What is the numeric value of ( address) -( start-address of section) ?
• Is the reference to an address “Program-Counter relative”?

In fact, every address as ever uses is expressed as ( section) + ( offset into section) Further, most expressions as computes have this section-relative nature.

In this manual we use the notation { secname N }to mean “offset N into section secname amp;.”

Apart from text, data and bss sections you need to know about the absolute section. When ld mixes partial programs, addresses in the absolute section remain unchanged. For example, address {absolute 0} is “relocated” to run-time address 0 by ld. Although the linker never arranges two partial programs' data sections with overlapping addresses after linking, by definition their absolute sections must overlap. Address {absolute 239} in one part of a program is always the same address when the program is running as address {absolute 239} in any other part of the program.

The idea of sections is extended to the undefined section. Any address whose section is unknown at assembly time is by definition rendered {undefined U }---where U is filled in later. Since numbers are always defined, the only way to generate an undefined address is to mention an undefined symbol. A reference to a named common block would be such a symbol: its value is unknown at assembly time so it has section undefined.

By analogy the word section is used to describe groups of sections in the linked program. ld puts all partial programs' text sections in contiguous addresses in the linked program. It is customary to refer to the text section of a program, meaning all the addresses of all partial programs' text sections. Likewise for data and bss sections.

Some sections are manipulated by ld; others are invented for use of as and have no meaning except during assembly.

ld deals with just four kinds of sections, summarized below.

named sections
	These sections hold your program. as and ld treat them as separate but equal sections. Anything you can say of one section is true of another. When the program is running, however, it is customary for the text section to be unalterable. The text section is often shared among processes: it contains instructions, constants and the like. The data section of a running program is usually alterable: for example, C variables would be stored in the data section.
bss section
	This section contains zeroed bytes when your program begins running. It is used to hold uninitialized variables or common storage. The length of each partial program's bss section is important, but because it starts out containing zeroed bytes there is no need to store explicit zero bytes in the object file. The bss section was invented to eliminate those explicit zeros from object files.
absolute section
	Address 0 of this section is always “relocated” to runtime address 0. This is useful if you want to refer to an address that ld must not change when relocating. In this sense we speak of absolute addresses being “unrelocatable”: they do not change during relocation.
undefined section
	This “section” is a catch-all for address references to objects not in the preceding sections.

An idealized example of three relocatable sections follows. The example uses the traditional section names .text and .data. Memory addresses are on the horizontal axis.

                      +-----+----+--+
partial program # 1:  |ttttt|dddd|00|
                      +-----+----+--+

                      text   data bss
                      seg.   seg. seg.

                      +---+---+---+
partial program # 2:  |TTT|DDD|000|
                      +---+---+---+

                      +--+---+-----+--+----+---+-----+~~
linked program:       |  |TTT|ttttt|  |dddd|DDD|00000|
                      +--+---+-----+--+----+---+-----+~~

    addresses:        0 ...

These sections are meant only for the internal use of as. They have no meaning at run-time. You do not really need to know about these sections for most purposes; but they can be mentioned in as warning messages, so it might be helpful to have an idea of their meanings to as. These sections are used to permit the value of every expression in your assembly language program to be a section-relative address.

ASSEMBLER-INTERNAL-LOGIC-ERROR!
	An internal assembler logic error has been found. This means there is a bug in the assembler.
expr section
	The assembler stores complex expression internally as combinations of symbols. When it needs to represent an expression as a symbol, it puts it in the expr section.

You may have separate groups of data in named sections that you want to end up near to each other in the object file, even though they are not contiguous in the assembler source. as allows you to use subsections for this purpose. Within each section, there can be numbered subsections with values from 0 to 8192. Objects assembled into the same subsection go into the object file together with other objects in the same subsection. For example, a compiler might want to store constants in the text section, but might not want to have them interspersed with the program being assembled. In this case, the compiler could issue a .text 0 before each section of code being output, and a .text 1 before each group of constants being output.

Subsections are optional. If you do not use subsections, everything goes in subsection number zero.

Subsections appear in your object file in numeric order, lowest numbered to highest. (All this to be compatible with other people's assemblers.) The object file contains no representation of subsections; ld and other programs that manipulate object files see no trace of them. They just see all your text subsections as a text section, and all your data subsections as a data section.

To specify which subsection you want subsequent statements assembled into, use a numeric argument to specify it, in a .text expression or a .data expression statement. You can also use the .subsection directive (see Section "SubSection") to specify a subsection: .subsection expression. Expression should be an absolute expression (see Section "Expressions"). If you just say .text then .text 0 is assumed. Likewise .data means .data 0. Assembly begins in text 0. For instance:

amp;.text 0     # The default subsection is text 0 anyway.
amp;.ascii "This lives in the first text subsection. *"
amp;.text 1
amp;.ascii "But this lives in the second text subsection."
amp;.data 0
amp;.ascii "This lives in the data section,"
amp;.ascii "in the first data subsection."
amp;.text 0
amp;.ascii "This lives in the first text section,"
amp;.ascii "immediately following the asterisk (*)."

Each section has a location counter incremented by one for every byte assembled into that section. Because subsections are merely a convenience restricted to as there is no concept of a subsection location counter. There is no way to directly manipulate a location counter---but the .align directive changes it, and any label definition captures its current value. The location counter of the section where statements are being assembled is said to be the active location counter.

The bss section is used for local common variable storage. You may allocate address space in the bss section, but you may not dictate data to load into it before your program executes. When your program starts running, all the contents of the bss section are zeroed bytes.

The .lcomm pseudo-op defines a symbol in the bss section; see Lcomm,, .lcomm amp;.

The .comm pseudo-op may be used to declare a common symbol, which is another form of uninitialized symbol; see Comm,, .comm amp;.

Symbols are a central concept: the programmer uses symbols to name things, the linker uses symbols to link, and the debugger uses symbols to debug.

" Warning: as does not place symbols in the object file in the same order they were declared. This may break some debuggers. "

A label is written as a symbol immediately followed by a colon :. The symbol then represents the current value of the active location counter, and is, for example, a suitable instruction operand. You are warned if you use the same symbol to represent two different locations: the first definition overrides any other definitions.

A symbol can be given an arbitrary value by writing a symbol, followed by an equals sign =, followed by an expression (see Section "Expressions"). This is equivalent to using the .set directive.See Section "Set". In the same way, using a double equals sign = = here represents an equivalent of the .eqv directive.See Section "Eqv".

Symbol names begin with a letter or with one of ._. On most machines, you can also use $ in symbol names; exceptions are noted in Machine Dependencies. That character may be followed by any string of digits, letters, dollar signs (unless otherwise noted for a particular target machine), and underscores.

Case of letters is significant: foo is a different symbol name than Foo.

Each symbol has exactly one name. Each name in an assembly language program refers to exactly one symbol. You may use that symbol name any number of times in a program.

Local Symbol Names

A local symbol is any symbol beginning with certain local label prefixes. By default, the local label prefix is .L for ELF systems or L for traditional a.out systems, but each target may have its own set of local label prefixes.

Local symbols are defined and used within the assembler, but they are normally not saved in object files. Thus, they are not visible when debugging. You may use the -L option (see Section "L") to retain the local symbols in the object files.

Local Labels

Local labels help compilers and programmers use names temporarily. They create symbols which are guaranteed to be unique over the entire scope of the input source code and which can be referred to by a simple notation. To define a local label, write a label of the form N: (where N represents any positive integer). To refer to the most recent previous definition of that label write Nb, using the same number as when you defined the label. To refer to the next definition of a local label, write Nf ---the b stands for “backwards” and the f stands for “forwards”.

There is no restriction on how you can use these labels, and you can reuse them too. So that it is possible to repeatedly define the same local label (using the same number N), although you can only refer to the most recently defined local label of that number (for a backwards reference) or the next definition of a specific local label for a forward reference. It is also worth noting that the first 10 local labels ( 0: amp;....Li Sy 9: ) are implemented in a slightly more efficient manner than the others.

Here is an example:

1:        branch 1f
2:        branch 1b
1:        branch 2f
2:        branch 1b

Which is the equivalent of:

label_1:  branch label_3
label_2:  branch label_1
label_3:  branch label_4
label_4:  branch label_3

Local label names are only a notational device. They are immediately transformed into more conventional symbol names before the assembler uses them. The symbol names are stored in the symbol table, appear in error messages, and are optionally emitted to the object file. The names are constructed using these parts:

local label prefix
	All local symbols begin with the system-specific local label prefix. Normally both as and ld forget symbols that start with the local label prefix. These labels are used for symbols you are never intended to see. If you use the -L option then as retains these symbols in the object file. If you also instruct ld to retain these symbols, you may use them in debugging.
number
	This is the number that was used in the local label definition. So if the label is written 55: then the number is 55.
C-B	This unusual character is included so you do not accidentally invent a symbol of the same name. The character has ASCII value of \002 (control-B).
ordinal number
	This is a serial number to keep the labels distinct. The first definition of 0: gets the number 1. The 15th definition of 0: gets the number 15, and so on. Likewise the first definition of 1: gets the number 1 and its 15th definition gets 15 as well.

So for example, the first 1: may be named .L1C-B1, and the 44th 3: may be named .L3C-B44.

Dollar Local Labels

as also supports an even more local form of local labels called dollar labels. These labels go out of scope (i.e., they become undefined) as soon as a non-local label is defined. Thus they remain valid for only a small region of the input source code. Normal local labels, by contrast, remain in scope for the entire file, or until they are redefined by another occurrence of the same local label.

Dollar labels are defined in exactly the same way as ordinary local labels, except that instead of being terminated by a colon, they are terminated by a dollar sign, e.g., 55$.

They can also be distinguished from ordinary local labels by their transformed names which use ASCII character \001 (control-A) as the magic character to distinguish them from ordinary labels. For example, the fifth definition of 6$ may be named .L6C-A5.

The special symbol . refers to the current address that as is assembling into. Thus, the expression melvin: .long. defines melvin to contain its own address. Assigning a value to . is treated the same as a .org directive. Thus, the expression .=.+4 is the same as saying .space 4.

Every symbol has, as well as its name, the attributes “Value” and “Type”. Depending on output format, symbols can also have auxiliary attributes. The detailed definitions are in a.out.h.

If you use a symbol without defining it, as assumes zero for all these attributes, and probably won't warn you. This makes the symbol an externally defined symbol, which is generally what you would want.

Value

The value of a symbol is (usually) 32 bits. For a symbol which labels a location in the text, data, bss or absolute sections the value is the number of addresses from the start of that section to the label. Naturally for text, data and bss sections the value of a symbol changes as ld changes section base addresses during linking. Absolute symbols' values do not change during linking: that is why they are called absolute.

The value of an undefined symbol is treated in a special way. If it is 0 then the symbol is not defined in this assembler source file, and ld tries to determine its value from other files linked into the same program. You make this kind of symbol simply by mentioning a symbol name without defining it. A non-zero value represents a .comm common declaration. The value is how much common storage to reserve, in bytes (addresses). The symbol refers to the first address of the allocated storage.

Type

The type attribute of a symbol contains relocation (section) information, any flag settings indicating that a symbol is external, and (optionally), other information for linkers and debuggers. The exact format depends on the object-code output format in use.

An expression specifies an address or numeric value. Whitespace may precede and/or follow an expression.

The result of an expression must be an absolute number, or else an offset into a particular section. If an expression is not absolute, and there is not enough information when as sees the expression to know its section, a second pass over the source program might be necessary to interpret the expression---but the second pass is currently not implemented. as aborts with an error message in this situation.

An empty expression has no value: it is just whitespace or null. Wherever an absolute expression is required, you may omit the expression, and as assumes a value of (absolute) 0. This is compatible with other assemblers.

An integer expression is one or more arguments delimited by operators.

Arguments

Arguments are symbols, numbers or subexpressions. In other contexts arguments are sometimes called “arithmetic operands”. In this manual, to avoid confusing them with the “instruction operands” of the machine language, we use the term “argument” to refer to parts of expressions only, reserving the word “operand” to refer only to machine instruction operands.

Symbols are evaluated to yield { section NNN }where section is one of text, data, bss, absolute, or undefined. NNN is a signed, 2's complement 32 bit integer.

Numbers are usually integers.

A number can be a flonum or biGNUm. In this case, you are warned that only the low order 32 bits are used, and as pretends these 32 bits are an integer. You may write integer-manipulating instructions that act on exotic constants, compatible with other assemblers.

Subexpressions are a left parenthesis ( followed by an integer expression, followed by a right parenthesis ); or a prefix operator followed by an argument.

Operators

Operators are arithmetic functions, like + or %. Prefix operators are followed by an argument. Infix operators appear between their arguments. Operators may be preceded and/or followed by whitespace.

Prefix Operator

as has the following prefix operators. They each take one argument, which must be absolute.

-	Negation. Two's complement negation.
~	Complementation. Bitwise not.

Infix Operators

Infix operators take two arguments, one on either side. Operators have precedence, but operations with equal precedence are performed left to right. Apart from + or [-], both arguments must be absolute, and the result is absolute.

1. Highest Precedence

   *	Multiplication.
   /	Division. Truncation is the same as the C operator /
   %	Remainder.
   <<
   	Shift Left. Same as the C operator <<.
   >>
   	Shift Right. Same as the C operator >>.

2. Intermediate precedence

   |	Bitwise Inclusive Or.
   &	Bitwise And.
   ^	Bitwise Exclusive Or.
   !	Bitwise Or Not.

3. Low Precedence

   +	Addition. If either argument is absolute, the result has the section of the other argument. You may not add together arguments from different sections.
   -	Subtraction. If the right argument is absolute, the result has the section of the left argument. If both arguments are in the same section, the result is absolute. You may not subtract arguments from different sections.
   ==	Is Equal To
   <> !=
   	Is Not Equal To
   <	Is Less Than
   >	Is Greater Than
   >=	Is Greater Than Or Equal To
   <=	Is Less Than Or Equal To The comparison operators can be used as infix operators. A true results has a value of -1 whereas a false result has a value of 0. Note, these operators perform signed comparisons.

4. Lowest Precedence

   &&
   	Logical And.
   ||	Logical Or. These two logical operations can be used to combine the results of sub expressions. Note, unlike the comparison operators a true result returns a value of 1 but a false results does still return 0. Also note that the logical or operator has a slightly lower precedence than logical and.

In short, it's only meaningful to add or subtract the offsets in an address; you can only have a defined section in one of the two arguments.

One day these directives won't work. They are included for compatibility with older assemblers.

.abort .line

-mcpu= processor[+ extension...]
	This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: arm1, arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, arm700i, arm710, arm710t, arm720, arm720t, arm740t, arm710c, arm7100, arm7500, arm7500fe, arm7t, arm7tdmi, arm7tdmi-s, arm8, arm810, strongarm, strongarm1, strongarm110, strongarm1100, strongarm1110, arm9, arm920, arm920t, arm922t, arm940t, arm9tdmi, arm9e, arm926e, arm926ej-s, arm946e-r0, arm946e, arm946e-s, arm966e-r0, arm966e, arm966e-s, arm968e-s, arm10t, arm10tdmi, arm10e, arm1020, arm1020t, arm1020e, arm1022e, arm1026ej-s, arm1136j-s, arm1136jf-s, arm1156t2-s, arm1156t2f-s, arm1176jz-s, arm1176jzf-s, mpcore, mpcorenovfp, cortex-a8, cortex-r4, cortex-m3, ep9312 (ARM920 with Cirrus Maverick coprocessor), i80200 (Intel XScale processor) iwmmxt (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and xscale. The special name all may be used to allow the assembler to accept instructions valid for any ARM processor. In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics that extend the processor using the co-processor instruction space. For example, -mcpu=arm920+maverick is equivalent to specifying -mcpu=ep9312. The following extensions are currently supported: +maverick +iwmmxt and +xscale.
-march= architecture[+ extension...]
	This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: armv1, armv2, armv2a, armv2s, armv3, armv3m, armv4, armv4xm, armv4t, armv4txm, armv5, armv5t, armv5txm, armv5te, armv5texp, armv6, armv6j, armv6k, armv6z, armv6zk, armv7, armv7-a, armv7-r, armv7-m, iwmmxt and xscale. If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. The architecture option can be extended with the same instruction set extension options as the -mcpu option.
-mfpu= floating-point-format
	This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit. The following format options are recognized: softfpa, fpe, fpe2, fpe3, fpa, fpa10, fpa11, arm7500fe, softvfp, softvfp+vfp, vfp, vfp10, vfp10-r0, vfp9, vfpxd, arm1020t, arm1020e, arm1136jf-s and maverick. In addition to determining which instructions are assembled, this option also affects the way in which the .double assembler directive behaves when assembling little-endian code. The default is dependent on the processor selected. For Architecture 5 or later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions.
-mthumb
	This option specifies that the assembler should start assembling Thumb instructions; that is, it should behave as though the file starts with a .code 16 directive.
-mthumb-interwork
	This option specifies that the output generated by the assembler should be marked as supporting interworking.
-mapcs[26|32]
	This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.
-matpcs
	This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can use this to determine the ABI being used by.
-mapcs-float
	This indicates the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers.
-mapcs-reentrant
	This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.
-mfloat-abi= abi
	This option specifies that the output generated by the assembler should be marked as using specified floating point ABI. The following values are recognized: soft, softfp and hard.
-meabi= ver
	This option specifies which EABI version the produced object files should conform to. The following values are recognized: GNU, 4 and 5.
-EB	This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
-EL	This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.
-k	This option specifies that the output of the assembler should be marked as position-independent code (PIC).

Special Characters

The presence of a @ on a line indicates the start of a comment that extends to the end of the current line. If a # appears as the first character of a line, the whole line is treated as a comment.

The ; character can be used instead of a newline to separate statements.

Either # or $ can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

Register Names

*TODO* Explain about ARM register naming, and the predefined names.

ARM relocation generation

Specific data relocations can be generated by putting the relocation name in parentheses after the symbol name. For example:

        .word foo(TARGET1)

This will generate an R_ARM_TARGET1 relocation against the symbol foo. The following relocations are supported: GOT, GOTOFF, TARGET1, TARGET2, SBREL, TLSGD, TLSLDM, TLSLDO, GOTTPOFF and TPOFF.

For compatibility with older toolchains the assembler also accepts (PLT) after branch targets. This will generate the deprecated R_ARM_PLT32 relocation.

Relocations for MOVW and MOVT instructions can be generated by prefixing the value with #:lower16: and #:upper16 respectively. For example to load the 32-bit address of foo into r0:

        MOVW r0, #:lower16:foo
        MOVT r0, #:upper16:foo

The ARM family uses ieee floating-point numbers.

.align expression [, expression]
	This is the generic .align directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatibility with ARM's own assembler.
name .req register name
	This creates an alias for register name called name. For example: foo .req r0
.unreq alias-name
	This undefines a register alias which was previously defined using the req, dn or qn directives. For example: foo .req r0 .unreq foo An error occurs if the name is undefined. Note - this pseudo op can be used to delete builtin in register name aliases (eg 'r0'). This should only be done if it is really necessary.
name .dn register name[ .type][ [index]] name .qn register name[ .type][ [index]]
	The dn and qn directives are used to create typed and/or indexed register aliases for use in Advanced SIMD Extension (Neon) instructions. The former should be used to create aliases of double-precision registers, and the latter to create aliases of quad-precision registers. If these directives are used to create typed aliases, those aliases can be used in Neon instructions instead of writing types after the mnemonic or after each operand. For example: x .dn d2.f32 y .dn d3.f32 z .dn d4.f32[1] vmul x,y,z This is equivalent to writing the following: vmul.f32 d2,d3,d4[1] Aliases created using dn or qn can be destroyed using unreq.
.code[16|32]
	This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.
.thumb	This performs the same action as .code 16.
.arm	This performs the same action as .code 32.
.force_thumb
	This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions
.thumb_func
	This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed. The presence of this directive also implies .thumb This directive is not neccessary when generating EABI objects. On these targets the encoding is implicit when generating Thumb code.
.thumb_set
	This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined). This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.
.ltorg	This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary). GAS maintains a separate literal pool for each section and each sub-section. The .ltorg directive will only affect the literal pool of the current section and sub-section. At the end of assembly all remaining, un-empty literal pools will automatically be dumped. Note - older versions of GAS would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools.
.pool	This is a synonym for .ltorg.
.unwind_fnstart
	Marks the start of a function with an unwind table entry.
.unwind_fnend
	Marks the end of a function with an unwind table entry. The unwind index table entry is created when this directive is processed. If no personality routine has been specified then standard personality routine 0 or 1 will be used, depending on the number of unwind opcodes required.
.cantunwind
	Prevents unwinding through the current function. No personality routine or exception table data is required or permitted.
.personality name
	Sets the personality routine for the current function to name.
.personalityindex index
	Sets the personality routine for the current function to the EABI standard routine number index
.handlerdata
	Marks the end of the current function, and the start of the exception table entry for that function. Anything between this directive and the .fnend directive will be added to the exception table entry. Must be preceded by a .personality or .personalityindex directive.
.save reglist
	Generate unwinder annotations to restore the registers in reglist. The format of reglist is the same as the corresponding store-multiple instruction. .save {r4, r5, r6, lr} stmfd sp!, {r4, r5, r6, lr} .save f4, 2 sfmfd f4, 2, [sp]! .save {d8, d9, d10} fstmdx sp!, {d8, d9, d10} .save {wr10, wr11} wstrd wr11, [sp, #-8]! wstrd wr10, [sp, #-8]! or .save wr11 wstrd wr11, [sp, #-8]! .save wr10 wstrd wr10, [sp, #-8]!
.vsave vfp-reglist
	Generate unwinder annotations to restore the VFP registers in vfp-reglist using FLDMD. Also works for VFPv3 registers that are to be restored using VLDM. The format of vfp-reglist is the same as the corresponding store-multiple instruction. .vsave {d8, d9, d10} fstmdd sp!, {d8, d9, d10} .vsave {d15, d16, d17} vstm sp!, {d15, d16, d17} Since FLDMX and FSTMX are now deprecated, this directive should be used in favour of .save for saving VFP registers for ARMv6 and above.
.pad # count
	Generate unwinder annotations for a stack adjustment of count bytes. A positive value indicates the function prologue allocated stack space by decrementing the stack pointer.
.movsp reg [, # offset]
	Tell the unwinder that reg contains an offset from the current stack pointer. If offset is not specified then it is assumed to be zero.
.setfp fpreg, spreg [, # offset]
	Make all unwinder annotations relaive to a frame pointer. Without this the unwinder will use offsets from the stack pointer. The syntax of this directive is the same as the sub or mov instruction used to set the frame pointer. spreg must be either sp or mentioned in a previous .movsp directive. amp;.movsp ip mov ip, sp amp;... amp;.setfp fp, ip, #4 sub fp, ip, #4
.raw offset, byte1, ...
	Insert one of more arbitary unwind opcode bytes, which are known to adjust the stack pointer by offset bytes. For example .unwind_raw 4, 0xb1, 0x01 is equivalent to .save {r0}
.cpu name
	Select the target processor. Valid values for name are the same as for the [-mcpu] commandline option.
.arch name
	Select the target architecture. Valid values for name are the same as for the [-march] commandline option.
.object_arch name
	Override the architecture recorded in the EABI object attribute section. Valid values for name are the same as for the .arch directive. Typically this is useful when code uses runtime detection of CPU features.
.fpu name
	Select the floating point unit to assemble for. Valid values for name are the same as for the [-mfpu] commandline option.
.eabi_attribute tag, value
	Set the EABI object attribute number tag to value. The value is either a number, string, or number, string depending on the tag.

as implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions.

NOP	nop This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.
LDR	ldr <register> , = <expression> If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.
ADR	adr <register> <label> This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.
ADRL	adrl <register> <label> This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long. If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

The ARM ELF specification requires that special symbols be inserted into object files to mark certain features:

$a	At the start of a region of code containing ARM instructions.
$t	At the start of a region of code containing THUMB instructions.
$d	At the start of a region of data.

The assembler will automatically insert these symbols for you - there is no need to code them yourself. Support for tagging symbols ($b, $f, $p and $m) which is also mentioned in the current ARM ELF specification is not implemented. This is because they have been dropped from the new EABI and so tools cannot rely upon their presence.

The i386 version as supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits.

The i386 version of as has a few machine dependent options:

--32 | --64
	Select the word size, either 32 bits or 64 bits. Selecting 32-bit implies Intel i386 architecture, while 64-bit implies AMD x86-64 architecture. These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).
-n	By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization.
--divide
	On SVR4-derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions. The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, or affect using # for starting a comment.
-march= CPU
	This option specifies an instruction set architecture for generating instructions. The following architectures are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, k6, k6_2, athlon, sledgehammer, opteron, k8, generic32 and generic64. This option only affects instructions generated by the assembler. The .arch directive will take precedent.
-mtune= CPU
	This option specifies a processor to optimize for. When used in conjunction with the [-march] option, only instructions of the processor specified by the [-march] option will be generated. Valid CPU values are identical to [-march= CPU].

as now supports assembly using Intel assembler syntax. .intel_syntax selects Intel mode, and .att_syntax switches back to the usual AT&T mode for compatibility with the output of gcc. Either of these directives may have an optional argument, prefix, or noprefix specifying whether registers require a % prefix. AT&T System V/386 assembler syntax is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are:

• AT&T immediate operands are preceded by $; Intel immediate operands are undelimited (Intel push 4 is AT&T pushl $4). AT&T register operands are preceded by %; Intel register operands are undelimited. AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by *; they are undelimited in Intel syntax.

• AT&T and Intel syntax use the opposite order for source and destination operands. Intel add eax, 4 is addl $4, %eax. The source, dest convention is maintained for compatibility with previous Unix assemblers. Note that instructions with more than one source operand, such as the enter instruction, do not have reversed order. i386-Bugs.

• In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of b, w, l and q specify byte (8-bit), word (16-bit), long (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes this by prefixing memory operands ( not the instruction mnemonics) with byte ptr, word ptr, dword ptr and qword ptr. Thus, Intel mov al, byte ptr foo is movb foo, %al in AT&T syntax.

• Immediate form long jumps and calls are lcall/ljmp $ section, $ offset in AT&T syntax; the Intel syntax is call/jmp far section: offset. Also, the far return instruction is lret $ stack-adjust in AT&T syntax; Intel syntax is ret far stack-adjust.

• The AT&T assembler does not provide support for multiple section programs. Unix style systems expect all programs to be single sections.

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters b, w, l and q specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, mov %ax, %bx is equivalent to movw %ax, %bx; also, mov $1, %bx is equivalent to movw $1, bx. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are movs... and movz... in AT&T syntax ( movsx and movzx in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, movsbl %al, %edx is AT&T syntax for “move sign extend from %al to %edx.” Possible suffixes, thus, are bl (from byte to long), bw (from byte to word), wl (from word to long), bq (from byte to quadruple word), wq (from word to quadruple word), and lq (from long to quadruple word).

The Intel-syntax conversion instructions

• cbw --- sign-extend byte in %al to word in %ax,

• cwde --- sign-extend word in %ax to long in %eax,

• cwd --- sign-extend word in %ax to long in %dx:%ax,

• cdq --- sign-extend dword in %eax to quad in %edx:%eax,

• cdqe --- sign-extend dword in %eax to quad in %rax (x86-64 only),

• cqo --- sign-extend quad in %rax to octuple in %rdx:%rax (x86-64 only),

are called cbtw, cwtl, cwtd, cltd, cltq, and cqto in AT&T naming. as accepts either naming for these instructions.

Far call/jump instructions are lcall and ljmp in AT&T syntax, but are call far and jump far in Intel convention.

Register operands are always prefixed with %. The 80386 registers consist of

• the 8 32-bit registers %eax (the accumulator), %ebx, %ecx, %edx, %edi, %esi, %ebp (the frame pointer), and %esp (the stack pointer).

• the 8 16-bit low-ends of these: %ax, %bx, %cx, %dx, %di, %si, %bp, and %sp.

• the 8 8-bit registers: %ah, %al, %bh, %bl, %ch, %cl, %dh, and %dl (These are the high-bytes and low-bytes of %ax, %bx, %cx, and %dx)

• the 6 section registers %cs (code section), %ds (data section), %ss (stack section), %es, %fs, and %gs.

• the 3 processor control registers %cr0, %cr2, and %cr3.

• the 6 debug registers %db0, %db1, %db2, %db3, %db6, and %db7.

• the 2 test registers %tr6 and %tr7.

• the 8 floating point register stack %st or equivalently %st(0), %st(1), %st(2), %st(3), %st(4), %st(5), %st(6), and %st(7). These registers are overloaded by 8 MMX registers %mm0, %mm1, %mm2, %mm3, %mm4, %mm5, %mm6 and %mm7.

• the 8 SSE registers registers %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6 and %xmm7.

The AMD x86-64 architecture extends the register set by:

• enhancing the 8 32-bit registers to 64-bit: %rax (the accumulator), %rbx, %rcx, %rdx, %rdi, %rsi, %rbp (the frame pointer), %rsp (the stack pointer)

• the 8 extended registers %r8 -- %r15.

• the 8 32-bit low ends of the extended registers: %r8d -- %r15d

• the 8 16-bit low ends of the extended registers: %r8w -- %r15w

• the 8 8-bit low ends of the extended registers: %r8b -- %r15b

• the 4 8-bit registers: %sil, %dil, %bpl, %spl.

• the 8 debug registers: %db8 -- %db15.

• the 8 SSE registers: %xmm8 -- %xmm15.

Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an “operand size” prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the scas (scan string) instruction is repeated with:

        repne scas %es:(%edi),%al

You may also place prefixes on the lines immediately preceding the instruction, but this circumvents checks that as does with prefixes, and will not work with all prefixes.

Here is a list of instruction prefixes:

• Section override prefixes cs, ds, ss, es, fs, gs. These are automatically added by specifying using the section : memory-operand form for memory references.

• Operand/Address size prefixes data16 and addr16 change 32-bit operands/addresses into 16-bit operands/addresses, while data32 and addr32 change 16-bit ones (in a .code16 section) into 32-bit operands/addresses. These prefixes must appear on the same line of code as the instruction they modify. For example, in a 16-bit .code16 section, you might write:

          addr32 jmpl *(%ebx)
  

• The bus lock prefix lock inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details).

• The wait for coprocessor prefix wait waits for the coprocessor to complete the current instruction. This should never be needed for the 80386/80387 combination.

• The rep, repe, and repne prefixes are added to string instructions to make them repeat %ecx times ( %cx times if the current address size is 16-bits).
• The rex family of prefixes is used by x86-64 to encode extensions to i386 instruction set. The rex prefix has four bits --- an operand size overwrite ( 64) used to change operand size from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the register set.

  You may write the rex prefixes directly. The rex64xyz instruction emits rex prefix with all the bits set. By omitting the 64, x, y or z you may write other prefixes as well. Normally, there is no need to write the prefixes explicitly, since gas will automatically generate them based on the instruction operands.

An Intel syntax indirect memory reference of the form

section:[base + index*scale + disp]

is translated into the AT&T syntax

section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand. If no scale is specified, scale is taken to be 1. section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a %. If you specify a section override which coincides with the default section register, as does not output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T:-4(%ebp), Intel:[ebp - 4]
	base is %ebp; disp is -4. section is missing, and the default section is used ( %ss for addressing with %ebp as the base register). index, scale are both missing.
AT&T:foo(,%eax,4), Intel:[foo + eax*4]
	index is %eax (scaled by a scale 4); disp is foo. All other fields are missing. The section register here defaults to %ds.
AT&T:foo(,1); Intel[foo]
	This uses the value pointed to by foo as a memory operand. Note that base and index are both missing, but there is only one ,. This is a syntactic exception.
AT&T:%gs:foo; Intelgs:foo
	This selects the contents of the variable foo with section register section being %gs.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with *. If no * is specified, as always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, long, or quadruple) with an instruction mnemonic suffix ( b, w, l or q, respectively).

The x86-64 architecture adds an RIP (instruction pointer relative) addressing. This addressing mode is specified by using rip as a base register. Only constant offsets are valid. For example:

AT&T:1234(%rip), Intel:[rip + 1234]
	Points to the address 1234 bytes past the end of the current instruction.
AT&T:symbol(%rip), Intel:[rip + symbol]
	Points to the symbol in RIP relative way, this is shorter than the default absolute addressing.

Other addressing modes remain unchanged in x86-64 architecture, except registers used are 64-bit instead of 32-bit.

Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the data16 instruction prefix), since the 80386 insists upon masking %eip to 16 bits after the word displacement is added. (See alsosee Section "i386-Arch")

Note that the jcxz, jecxz, loop, loopz, loope, loopnz and loopne instructions only come in byte displacements, so that if you use these instructions ( gcc does not use them) you may get an error message (and incorrect code). The AT&T 80386 assembler tries to get around this problem by expanding jcxz foo to

         jcxz cx_zero
         jmp cx_nonzero
cx_zero: jmp foo
cx_nonzero:

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.

• Floating point constructors are .float or .single, .double, and .tfloat for 32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes s, l, and t. t stands for 80-bit (ten byte) real. The 80387 only supports this format via the fldt (load 80-bit real to stack top) and fstpt (store 80-bit real and pop stack) instructions.

• Integer constructors are .word, .long or .int, and .quad for the 16-, 32-, and 64-bit integer formats. The corresponding instruction mnemonic suffixes are s (single), l (long), and q (quad). As with the 80-bit real format, the 64-bit q format is only present in the fildq (load quad integer to stack top) and fistpq (store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes. fstl %st, %st(1) will give a warning, and be assembled as if you wrote fst %st, %st(1), since all register to register operations use 80-bit floating point operands. (Contrast this with fstl %st, mem, which converts %st from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location mem)

as supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, as does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called %mm0, %mm1, amp;... %mm7. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

While as normally writes only “pure” 32-bit i386 code or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a .code16 or .code16gcc directive before the assembly language instructions to be run in 16-bit mode. You can switch as back to writing normal 32-bit code with the .code32 directive.

.code16gcc provides experimental support for generating 16-bit code from gcc, and differs from .code16 in that call, ret, enter, leave, push, pop, pusha, popa, pushf, and popf instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. .code16gcc also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.

The code which as generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require as to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes 66 6a 04, which pushes the value 4 onto the stack, decrementing %esp by 2.

        pushw $4

The same code in a 16-bit code section would generate the machine opcode bytes 6a 04 (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

        fsub %st,%st(3)

results in %st(3) being updated to %st - %st(3) rather than the expected %st(3) - %st. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is %st and the destination register is %st(i).

as may be told to assemble for a particular CPU (sub-)architecture with the .arch cpu_type directive. This directive enables a warning when gas detects an instruction that is not supported on the CPU specified. The choices for cpu_type are:

i8086	i186	i286	i386
i486	i586	i686	pentium
pentiumpro	pentiumii	pentiumiii	pentium4
prescott	nocona	core	core2
amdfam10
k6	athlon	sledgehammer	k8
amp;.mmx	.sse	.sse2	.sse3
amp;.ssse3	.sse4.1	.sse4.2	.sse4
amp;.sse4a	.3dnow	.3dnowa	.padlock
amp;.pacifica	.svme	.abm

Apart from the warning, there are only two other effects on as operation; Firstly, if you specify a CPU other than i486, then shift by one instructions such as sarl $1, %eax will automatically use a two byte opcode sequence. The larger three byte opcode sequence is used on the 486 (and when no architecture is specified) because it executes faster on the 486. Note that you can explicitly request the two byte opcode by writing sarl %eax. Secondly, if you specify i8086, i186, or i286, and .code16 or .code16gcc then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target.

Following the CPU architecture (but not a sub-architecture, which are those starting with a dot), you may specify jumps or nojumps to control automatic promotion of conditional jumps. jumps is the default, and enables jump promotion; All external jumps will be of the long variety, and file-local jumps will be promoted as necessary. (see Section "i386-Jumps") nojumps leaves external conditional jumps as byte offset jumps, and warns about file-local conditional jumps that as promotes. Unconditional jumps are treated as for jumps.

For example

 .arch i8086,nojumps

There is some trickery concerning the mul and imul instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies (base opcode 0xf6; extension 4 for mul and 5 for imul) can be output only in the one operand form. Thus, imul %ebx, %eax does not select the expanding multiply; the expanding multiply would clobber the %edx register, and this would confuse gcc output. Use imul %ebx to get the 64-bit product in %edx:%eax.

We have added a two operand form of imul when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying %eax by 69, for example, can be done with imul $69, %eax rather than imul $69, %eax, %eax.

-mconstant-gp
	This option instructs the assembler to mark the resulting object file as using the “constant GP” model. With this model, it is assumed that the entire program uses a single global pointer (GP) value. Note that this option does not in any fashion affect the machine code emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP flag in the ELF file header.
-mauto-pic
	This option instructs the assembler to mark the resulting object file as using the “constant GP without function descriptor” data model. This model is like the “constant GP” model, except that it additionally does away with function descriptors. What this means is that the address of a function refers directly to the function's code entry-point. Normally, such an address would refer to a function descriptor, which contains both the code entry-point and the GP-value needed by the function. Note that this option does not in any fashion affect the machine code emitted by the assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
-milp32 -milp64 -mlp64 -mp64
	These options select the data model. The assembler defaults to -mlp64 (LP64 data model).
-mle -mbe
	These options select the byte order. The -mle option selects little-endian byte order (default) and -mbe selects big-endian byte order. Note that IA-64 machine code always uses little-endian byte order.
-mtune=itanium1 -mtune=itanium2
	Tune for a particular IA-64 CPU, itanium1 or itanium2. The default is itanium2.
-munwind-check=warning -munwind-check=error
	These options control what the assembler will do when performing consistency checks on unwind directives. -munwind-check=warning will make the assembler issue a warning when an unwind directive check fails. This is the default. -munwind-check=error will make the assembler issue an error when an unwind directive check fails.
-mhint.b=ok -mhint.b=warning -mhint.b=error
	These options control what the assembler will do when the hint.b instruction is used. -mhint.b=ok will make the assembler accept hint.b. -mint.b=warning will make the assembler issue a warning when hint.b is used. -mhint.b=error will make the assembler treat hint.b as an error, which is the default.
-x -xexplicit
	These options turn on dependency violation checking.
-xauto
	This option instructs the assembler to automatically insert stop bits where necessary to remove dependency violations. This is the default mode.
-xnone
	This option turns off dependency violation checking.
-xdebug
	This turns on debug output intended to help tracking down bugs in the dependency violation checker.
-xdebugn
	This is a shortcut for -xnone -xdebug.
-xdebugx
	This is a shortcut for -xexplicit -xdebug.

The assembler syntax closely follows the IA-64 Assembly Language Reference Guide.

Special Characters

// is the line comment token.

; can be used instead of a newline to separate statements.

Register Names

The 128 integer registers are referred to as r n. The 128 floating-point registers are referred to as f n. The 128 application registers are referred to as ar n. The 128 control registers are referred to as cr n. The 64 one-bit predicate registers are referred to as p n. The 8 branch registers are referred to as b n. In addition, the assembler defines a number of aliases: gp ( r1), sp ( r12), rp ( b0), ret0 ( r8), ret1 ( r9), ret2 ( r10), ret3 ( r9), farg n ( f8+ n), and fret n ( f8+ n).

For convenience, the assembler also defines aliases for all named application and control registers. For example, ar.bsp refers to the register backing store pointer ( ar17). Similarly, cr.eoi refers to the end-of-interrupt register ( cr67).

IA-64 Processor-Status-Register (PSR) Bit Names

The assembler defines bit masks for each of the bits in the IA-64 processor status register. For example, psr.ic corresponds to a value of 0x2000. These masks are primarily intended for use with the ssm / sum and rsm / rum instructions, but they can be used anywhere else where an integer constant is expected.

GNU as for mips architectures supports several different mips processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For information about the mips instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of mips assembly conventions, see “Appendix D: Assembly Language Programming” in the same work.

The mips configurations of GNU as support these special options:

-G num
	This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ecoff format. The default value is 8.
-EB -EL
	Any mips configuration of as can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use -EB to select big-endian output, and -EL for little-endian.
-KPIC	Generate SVR4-style PIC. This option tells the assembler to generate SVR4-style position-independent macro expansions. It also tells the assembler to mark the output file as PIC.
-mvxworks-pic
	Generate VxWorks PIC. This option tells the assembler to generate VxWorks-style position-independent macro expansions.
-mips1 -mips2 -mips3 -mips4 -mips5 -mips32 -mips32r2 -mips64 -mips64r2
	Generate code for a particular MIPS Instruction Set Architecture level. -mips1 corresponds to the r2000 and r3000 processors, -mips2 to the r6000 processor, -mips3 to the r4000 processor, and -mips4 to the r8000 and r10000 processors. -mips5, -mips32, -mips32r2, -mips64, and -mips64r2 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also switch instruction sets during the assembly; see MIPS ISA, Directives to override the ISA level.
-mgp32 -mfp32
	Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers. The .set gp=32 and .set fp=32 directives allow the size of registers to be changed for parts of an object. The default value is restored by .set gp=default and .set fp=default. On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.
-mgp64 -mfp64
	Assume that 64-bit registers are available. This is provided in the interests of symmetry with -mgp32 and -mfp32. The .set gp=64 and .set fp=64 directives allow the size of registers to be changed for parts of an object. The default value is restored by .set gp=default and .set fp=default.
-mips16 -no-mips16
	Generate code for the MIPS 16 processor. This is equivalent to putting .set mips16 at the start of the assembly file. -no-mips16 turns off this option.
-msmartmips -mno-smartmips
	Enables the SmartMIPS extensions to the MIPS32 instruction set, which provides a number of new instructions which target smartcard and cryptographic applications. This is equivalent to putting .set smartmips at the start of the assembly file. -mno-smartmips turns off this option.
-mips3d -no-mips3d
	Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.
-mdmx -no-mdmx
	Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.
-mdsp -mno-dsp
	Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.
-mdspr2 -mno-dspr2
	Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.
-mmt -mno-mt
	Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option.
-mfix7000 -mno-fix7000
	Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
-mfix-vr4120 -no-mfix-vr4120
	Insert nops to work around certain VR4120 errata. This option is intended to be used on GCC-generated code: it is not designed to catch all problems in hand-written assembler code.
-mfix-vr4130 -no-mfix-vr4130
	Insert nops to work around the VR4130 mflo / mfhi errata.
-m4010 -no-m4010
	Generate code for the LSI r4010 chip. This tells the assembler to accept the r4010 specific instructions ( addciu, ffc, etc.), and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4010 turns off this option.
-m4650 -no-m4650
	Generate code for the MIPS r4650 chip. This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.
-m3900 -no-m3900 -m4100 -no-m4100
	For each option -m nnnn, generate code for the MIPS r nnnn chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.
-march= cpu
	Generate code for a particular MIPS cpu. It is exactly equivalent to -m cpu, except that there are more value of cpu understood. Valid cpu value are: " 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k, m4kp, 24kc, 24kf, 24kx, 24kec, 24kef, 24kex, 34kc, 34kf, 34kx, 74kc, 74kf, 74kx, 5kc, 5kf, 20kc, 25kf, sb1, sb1a "
-mtune= cpu
	Schedule and tune for a particular MIPS cpu. Valid cpu values are identical to -march= cpu.
-mabi= abi
	Record which ABI the source code uses. The recognized arguments are: 32, n32, o64, 64 and eabi.
-msym32 -mno-sym32
	Equivalent to adding .set sym32 or .set nosym32 to the beginning of the assembler input.See Section "MIPS symbol sizes".
-nocpp
	This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With GNU as, there is no need for -nocpp, because the GNU assembler itself never runs the C preprocessor.
--construct-floats --no-construct-floats
	The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers. By default --construct-floats is selected, allowing construction of these floating point constants.
--trap --no-break
	as automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes as to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.
--break --no-trap
	Generate code to take a break exception rather than a trap exception when an error is detected. This is the default.
-mpdr -mno-pdr
	Control generation of .pdr sections. Off by default on IRIX, on elsewhere.
-mshared -mno-shared
	When generating code using the Unix calling conventions (selected by -KPIC or -mcall_shared), gas will normally generate code which can go into a shared library. The -mno-shared option tells gas to generate code which uses the calling convention, but can not go into a shared library. The resulting code is slightly more efficient. This option only affects the handling of the .cpload and .cpsetup pseudo-ops.

Assembling for a mips ecoff target supports some additional sections besides the usual .text, .data and .bss. The additional sections are .rdata, used for read-only data, .sdata, used for small data, and .sbss, used for small common objects.

When assembling for ecoff, the assembler uses the $gp ( $28) register to form the address of a “small object”. Any object in the .sdata or .sbss sections is considered “small” in this sense. For external objects, or for objects in the .bss section, you can use the gcc -G option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp. Passing -G 0 to as prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case). The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it. The size of an external object may be set with the .extern directive. For example, .extern sym,4 declares that the object at sym is 4 bytes in length, whie leaving sym otherwise undefined.

Using small ecoff objects requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code). mips ecoff assembly code must not modify the $gp register.

mips ecoff as supports several directives used for generating debugging information which are not support by traditional mips assemblers. These are .def, .endef, .dim, .file, .scl, .size, .tag, .type, .val, .stabd, .stabn, and .stabs. The debugging information generated by the three .stab directives can only be read by gdb, not by traditional mips debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers!

The n64 ABI allows symbols to have any 64-bit value. Although this provides a great deal of flexibility, it means that some macros have much longer expansions than their 32-bit counterparts. For example, the non-PIC expansion of dla $4,sym is usually:

lui     $4,%highest(sym)
lui     $1,%hi(sym)
daddiu  $4,$4,%higher(sym)
daddiu  $1,$1,%lo(sym)
dsll32  $4,$4,0
daddu   $4,$4,$1

whereas the 32-bit expansion is simply:

lui     $4,%hi(sym)
daddiu  $4,$4,%lo(sym)

n64 code is sometimes constructed in such a way that all symbolic constants are known to have 32-bit values, and in such cases, it's preferable to use the 32-bit expansion instead of the 64-bit expansion.

You can use the .set sym32 directive to tell the assembler that, from this point on, all expressions of the form symbol or symbol + offset have 32-bit values. For example:

amp;.set sym32
dla     $4,sym
lw      $4,sym+16
sw      $4,sym+0x8000($4)

will cause the assembler to treat sym, sym+16 and sym+0x8000 as 32-bit values. The handling of non-symbolic addresses is not affected.

The directive .set nosym32 ends a .set sym32 block and reverts to the normal behavior. It is also possible to change the symbol size using the command-line options [-msym32] and [-mno-sym32].

These options and directives are always accepted, but at present, they have no effect for anything other than n64.

GNU as supports an additional directive to change the mips Instruction Set Architecture level on the fly: .set mips n. n should be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other than 0 make the assembler accept instructions for the corresponding isa level, from that point on in the assembly. .set mips n affects not only which instructions are permitted, but also how certain macros are expanded. .set mips0 restores the isa level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific mips3 instructions while assembling in 32 bit mode. Use this directive with care!

The .set arch= cpu directive provides even finer control. It changes the effective CPU target and allows the assembler to use instructions specific to a particular CPU. All CPUs supported by the -march command line option are also selectable by this directive. The original value is restored by .set arch=default.

The directive .set mips16 puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use .set nomips16 to return to normal 32 bit mode.

Traditional mips assemblers do not support this directive.

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary. The directive .set noautoextend will turn this off. When .set noautoextend is in effect, any 32 bit instruction must be explicitly extended with the .e modifier (e.g., li.e $4,1000). The directive .set autoextend may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode. Traditional mips assemblers do not support this directive.

The .insn directive tells as that the following data is actually instructions. This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, as automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set. The .set push directive saves the current settings on a stack. The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional mips assemblers do not support these directives.

The directive .set mips3d makes the assembler accept instructions from the MIPS-3D Application Specific Extension from that point on in the assembly. The .set nomips3d directive prevents MIPS-3D instructions from being accepted.

The directive .set smartmips makes the assembler accept instructions from the SmartMIPS Application Specific Extension to the MIPS32 isa from that point on in the assembly. The .set nosmartmips directive prevents SmartMIPS instructions from being accepted.

The directive .set mdmx makes the assembler accept instructions from the MDMX Application Specific Extension from that point on in the assembly. The .set nomdmx directive prevents MDMX instructions from being accepted.

The directive .set dsp makes the assembler accept instructions from the DSP Release 1 Application Specific Extension from that point on in the assembly. The .set nodsp directive prevents DSP Release 1 instructions from being accepted.

The directive .set dspr2 makes the assembler accept instructions from the DSP Release 2 Application Specific Extension from that point on in the assembly. This dirctive implies .set dsp. The .set nodspr2 directive prevents DSP Release 2 instructions from being accepted.

The directive .set mt makes the assembler accept instructions from the MT Application Specific Extension from that point on in the assembly. The .set nomt directive prevents MT instructions from being accepted.

Traditional mips assemblers do not support these directives.

The PowerPC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.

The following table lists all available PowerPC options.

-mpwrx | -mpwr2
	Generate code for POWER/2 (RIOS2).
-mpwr	Generate code for POWER (RIOS1)
-m601	Generate code for PowerPC 601.
-mppc, -mppc32, -m603, -m604
	Generate code for PowerPC 603/604.
-m403, -m405
	Generate code for PowerPC 403/405.
-m440	Generate code for PowerPC 440. BookE and some 405 instructions.
-m7400, -m7410, -m7450, -m7455
	Generate code for PowerPC 7400/7410/7450/7455.
-mppc64, -m620
	Generate code for PowerPC 620/625/630.
-me500, -me500x2
	Generate code for Motorola e500 core complex.
-mspe	Generate code for Motorola SPE instructions.
-mppc64bridge
	Generate code for PowerPC 64, including bridge insns.
-mbooke64
	Generate code for 64-bit BookE.
-mbooke, mbooke32
	Generate code for 32-bit BookE.
-me300
	Generate code for PowerPC e300 family.
-maltivec
	Generate code for processors with AltiVec instructions.
-mpower4
	Generate code for Power4 architecture.
-mpower5
	Generate code for Power5 architecture.
-mpower6
	Generate code for Power6 architecture.
-mcell
	Generate code for Cell Broadband Engine architecture.
-mcom	Generate code Power/PowerPC common instructions.
-many	Generate code for any architecture (PWR/PWRX/PPC).
-mregnames
	Allow symbolic names for registers.
-mno-regnames
	Do not allow symbolic names for registers.
-mrelocatable
	Support for GCC's -mrelocatable option.
-mrelocatable-lib
	Support for GCC's -mrelocatable-lib option.
-memb	Set PPC_EMB bit in ELF flags.
-mlittle, -mlittle-endian
	Generate code for a little endian machine.
-mbig, -mbig-endian
	Generate code for a big endian machine.
-msolaris
	Generate code for Solaris.
-mno-solaris
	Do not generate code for Solaris.

A number of assembler directives are available for PowerPC. The following table is far from complete.

.machine string
	This directive allows you to change the machine for which code is generated. string may be any of the -m cpu selection options (without the -m) enclosed in double quotes, push, or pop. .machine push saves the currently selected cpu, which may be restored with .machine pop.

The SPARC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.

By default, as assumes the core instruction set (SPARC v6), but “bumps” the architecture level as needed: it switches to successively higher architectures as it encounters instructions that only exist in the higher levels.

If not configured for SPARC v9 ( sparc64-*-*) GAS will not bump passed sparclite by default, an option must be passed to enable the v9 instructions.

GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.

-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite -Av8plus | -Av8plusa | -Av9 | -Av9a
	Use one of the -A options to select one of the SPARC architectures explicitly. If you select an architecture explicitly, as reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level. -Av8plus and -Av8plusa select a 32 bit environment. -Av9 and -Av9a select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support. -Av8plusa and -Av9a enable the SPARC V9 instruction set with UltraSPARC extensions.
-xarch=v8plus | -xarch=v8plusa
	For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
-bump	Warn whenever it is necessary to switch to another level. If an architecture level is explicitly requested, GAS will not issue warnings until that level is reached, and will then bump the level as required (except between incompatible levels).
-32 | -64
	Select the word size, either 32 bits or 64 bits. These options are only available with the ELF object file format, and require that the necessary BFD support has been included.

SPARC GAS normally permits data to be misaligned. For example, it permits the .long pseudo-op to be used on a byte boundary. However, the native SunOS and Solaris assemblers issue an error when they see misaligned data.

You can use the --enforce-aligned-data option to make SPARC GAS also issue an error about misaligned data, just as the SunOS and Solaris assemblers do.

The --enforce-aligned-data option is not the default because gcc issues misaligned data pseudo-ops when it initializes certain packed data structures (structures defined using the packed attribute). You may have to assemble with GAS in order to initialize packed data structures in your own code.

The Sparc uses ieee floating-point numbers.

The Sparc version of as supports the following additional machine directives:

.align	This must be followed by the desired alignment in bytes.
.common
	This must be followed by a symbol name, a positive number, and bss. This behaves somewhat like .comm, but the syntax is different.
.half	This is functionally identical to .short.
.nword	On the Sparc, the .nword directive produces native word sized value, ie. if assembling with -32 it is equivalent to .word, if assembling with -64 it is equivalent to .xword.
.proc	This directive is ignored. Any text following it on the same line is also ignored.
.register
	This directive declares use of a global application or system register. It must be followed by a register name %g2, %g3, %g6 or %g7, comma and the symbol name for that register. If symbol name is #scratch, it is a scratch register, if it is #ignore, it just suppresses any errors about using undeclared global register, but does not emit any information about it into the object file. This can be useful e.g. if you save the register before use and restore it after.
.reserve
	This must be followed by a symbol name, a positive number, and bss. This behaves somewhat like .lcomm, but the syntax is different.
.seg	This must be followed by text, data, or data1. It behaves like .text, .data, or .data 1.
.skip	This is functionally identical to the .space directive.
.word	On the Sparc, the .word directive produces 32 bit values, instead of the 16 bit values it produces on many other machines.
.xword	On the Sparc V9 processor, the .xword directive produces 64 bit values.

Your bug reports play an essential role in making as reliable.

Reporting a bug may help you by bringing a solution to your problem, or it may not. But in any case the principal function of a bug report is to help the entire community by making the next version of as work better. Bug reports are your contribution to the maintenance of as.

In order for a bug report to serve its purpose, you must include the information that enables us to fix the bug.

If you are not sure whether you have found a bug, here are some guidelines:

• If the assembler gets a fatal signal, for any input whatever, that is a as bug. Reliable assemblers never crash.

• If as produces an error message for valid input, that is a bug.

• If as does not produce an error message for invalid input, that is a bug. However, you should note that your idea of “invalid input” might be our idea of “an extension” or “support for traditional practice”.

• If you are an experienced user of assemblers, your suggestions for improvement of as are welcome in any case.

A number of companies and individuals offer support for GNU products. If you obtained as from a support organization, we recommend you contact that organization first.

You can find contact information for many support companies and individuals in the file etc/SERVICE in the GNU Emacs distribution.

The fundamental principle of reporting bugs usefully is this: report all the facts. If you are not sure whether to state a fact or leave it out, state it!

Often people omit facts because they think they know what causes the problem and assume that some details do not matter. Thus, you might assume that the name of a symbol you use in an example does not matter. Well, probably it does not, but one cannot be sure. Perhaps the bug is a stray memory reference which happens to fetch from the location where that name is stored in memory; perhaps, if the name were different, the contents of that location would fool the assembler into doing the right thing despite the bug. Play it safe and give a specific, complete example. That is the easiest thing for you to do, and the most helpful.

Keep in mind that the purpose of a bug report is to enable us to fix the bug if it is new to us. Therefore, always write your bug reports on the assumption that the bug has not been reported previously.

Sometimes people give a few sketchy facts and ask, “Does this ring a bell?” This cannot help us fix a bug, so it is basically useless. We respond by asking for enough details to enable us to investigate. You might as well expedite matters by sending them to begin with.

To enable us to fix the bug, you should include all these things:

• The version of as. as announces it if you start it with the --version argument.

  Without this, we will not know whether there is any point in looking for the bug in the current version of as.

• Any patches you may have applied to the as source.

• The type of machine you are using, and the operating system name and version number.

• What compiler (and its version) was used to compile as ---e.g. “ gcc-2.7 ”amp;.

• The command arguments you gave the assembler to assemble your example and observe the bug. To guarantee you will not omit something important, list them all. A copy of the Makefile (or the output from make) is sufficient.

  If we were to try to guess the arguments, we would probably guess wrong and then we might not encounter the bug.

• A complete input file that will reproduce the bug. If the bug is observed when the assembler is invoked via a compiler, send the assembler source, not the high level language source. Most compilers will produce the assembler source when run with the -S option. If you are using gcc, use the options -v --save-temps; this will save the assembler source in a file with an extension of .s, and also show you exactly how as is being run.

• A description of what behavior you observe that you believe is incorrect. For example, “It gets a fatal signal.”

  Of course, if the bug is that as gets a fatal signal, then we will certainly notice it. But if the bug is incorrect output, we might not notice unless it is glaringly wrong. You might as well not give us a chance to make a mistake.

  Even if the problem you experience is a fatal signal, you should still say so explicitly. Suppose something strange is going on, such as, your copy of as is out of sync, or you have encountered a bug in the C library on your system. (This has happened!) Your copy might crash and ours would not. If you told us to expect a crash, then when ours fails to crash, we would know that the bug was not happening for us. If you had not told us to expect a crash, then we would not be able to draw any conclusion from our observations.

• If you wish to suggest changes to the as source, send us context diffs, as generated by diff with the -u, -c, or -p option. Always send diffs from the old file to the new file. If you even discuss something in the as source, refer to it by context, not by line number.

  The line numbers in our development sources will not match those in your sources. Your line numbers would convey no useful information to us.

Here are some things that are not necessary:

• A description of the envelope of the bug.

  Often people who encounter a bug spend a lot of time investigating which changes to the input file will make the bug go away and which changes will not affect it.

  This is often time consuming and not very useful, because the way we will find the bug is by running a single example under the debugger with breakpoints, not by pure deduction from a series of examples. We recommend that you save your time for something else.

  Of course, if you can find a simpler example to report instead of the original one, that is a convenience for us. Errors in the output will be easier to spot, running under the debugger will take less time, and so on.

  However, simplification is not vital; if you do not want to do this, report the bug anyway and send us the entire test case you used.

• A patch for the bug.

  A patch for the bug does help us if it is a good one. But do not omit the necessary information, such as the test case, on the assumption that a patch is all we need. We might see problems with your patch and decide to fix the problem another way, or we might not understand it at all.

  Sometimes with a program as complicated as as it is very hard to construct an example that will make the program follow a certain path through the code. If you do not send us the example, we will not be able to construct one, so we will not be able to verify that the bug is fixed.

  And if we cannot understand what bug you are trying to fix, or why your patch should be an improvement, we will not install it. A test case will help us to understand.

• A guess about what the bug is or what it depends on.

  Such guesses are usually wrong. Even we cannot guess right about such things without first using the debugger to find the facts.

If you have contributed to GAS and your name isn't listed here, it is not meant as a slight. We just don't know about it. Send mail to the maintainer, and we'll correct the situation. Currently the maintainer is Ken Raeburn (email address raeburn@cyGNUs.com).

Dean Elsner wrote the original GNU assembler for the VAX.

Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug information and the 68k series machines, most of the preprocessing pass, and extensive changes in messages.c, input-file.c, write.c.

K. Richard Pixley maintained GAS for a while, adding various enhancements and many bug fixes, including merging support for several processors, breaking GAS up to handle multiple object file format back ends (including heavy rewrite, testing, an integration of the coff and b.out back ends), adding configuration including heavy testing and verification of cross assemblers and file splits and renaming, converted GAS to strictly ANSI C including full prototypes, added support for m680[34]0 and cpu32, did considerable work on i960 including a COFF port (including considerable amounts of reverse engineering), a SPARC opcode file rewrite, DECstation, rs6000, and hp300hpux host ports, updated “know” assertions and made them work, much other reorganization, cleanup, and lint.

Ken Raeburn wrote the high-level BFD interface code to replace most of the code in format-specific I/O modules.

The original VMS support was contributed by David L. Kashtan. Eric Youngdale has done much work with it since.

The Intel 80386 machine description was written by Eliot Dresselhaus.

Minh Tran-Le at IntelliCorp contributed some AIX 386 support.

The Motorola 88k machine description was contributed by Devon Bowen of Buffalo University and Torbjorn Granlund of the Swedish Institute of Computer Science.

Keith Knowles at the Open Software Foundation wrote the original MIPS back end ( tc-mips.c, tc-mips.h), and contributed Rose format support (which hasn't been merged in yet). Ralph Campbell worked with the MIPS code to support a.out format.

Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, tc-h8300), and IEEE 695 object file format (obj-ieee), was written by Steve Chamberlain of CyGNUs Support. Steve also modified the COFF back end to use BFD for some low-level operations, for use with the H8/300 and AMD 29k targets.

John Gilmore built the AMD 29000 support, added .include support, and simplified the configuration of which versions accept which directives. He updated the 68k machine description so that Motorola's opcodes always produced fixed-size instructions (e.g., jsr), while synthetic instructions remained shrinkable ( jbsr). John fixed many bugs, including true tested cross-compilation support, and one bug in relaxation that took a week and required the proverbial one-bit fix.

Ian Lance Taylor of CyGNUs Support merged the Motorola and MIT syntax for the 68k, completed support for some COFF targets (68k, i386 SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and PowerPC assembler, and made a few other minor patches.

Steve Chamberlain made GAS able to generate listings.

Hewlett-Packard contributed support for the HP9000/300.

Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF object formats). This work was supported by both the Center for Software Science at the University of Utah and CyGNUs Support.

Support for ELF format files has been worked on by Mark Eichin of CyGNUs Support (original, incomplete implementation for SPARC), Pete Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn of CyGNUs Support (sparc, and some initial 64-bit support).

Linas Vepstas added GAS support for the ESA/390 “IBM 370” architecture.

Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD support for openVMS/Alpha.

Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic* flavors.

David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica, Inc. added support for Xtensa processors.

Several engineers at CyGNUs Support have also provided many small bug fixes and configuration enhancements.

Many others have contributed large or small bugfixes and enhancements. If you have contributed significant work and are not mentioned on this list, and want to be, let us know. Some of the history has been lost; we are not intentionally leaving anyone out.

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