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The Cherry View SoC has 5 banks of GPIO pins, NORTH, EAST, SOUTHEAST, SOUTHWEST and VIRTUAL. All but VIRTUAL are exposed to userland as /dev/gpiocN, where N is 0-3. Pins in each bank are pre-named to match names in the Intel® Atom⢠Z8000 Processor Series Vol 2
Intel® Atom⢠Z8000 Processor Series Vol 1,
Intel® Atom⢠Z8000 Processor Series Vol 2,
CHVGPIO (4) | November 17, 2017 |
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