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With the
foo0@pci0:0:4:0: class=0x010000 card=0x00000000 chip=0x000f1000 rev=0x01 hdr=0x00 bar0@pci0:0:5:0: class=0x000100 card=0x00000000 chip=0x88c15333 rev=0x00 hdr=0x00 none0@pci0:0:6:0: class=0x020000 card=0x00000000 chip=0x802910ec rev=0x00 hdr=0x00
The first column gives the driver name, unit number, and selector . If there is no driver attached to the PCI device in question, the driver name will be "none". Unit numbers for detached devices start at zero and are incremented for each detached device that is encountered. The selector is in a form which may directly be used for the other forms of the command. The second column is the class code, with the class byte printed as two hex digits, followed by the sub-class and the interface bytes. The third column gives the contents of the subvendorid register, introduced in revision 2.1 of the PCI standard. Note that it will be 0 for older cards. The field consists of the card ID in the upper half and the card vendor ID in the lower half of the value.
The fourth column contains the chip device ID, which identifies the chip this card is based on. It consists of two fields, identifying the chip and its vendor, as above. The fifth column prints the chip's revision. The sixth column describes the header type. Currently assigned header types include 0 for most devices, 1 for PCI to PCI bridges, and 2 for PCI to CardBus bridges. If the most significant bit of the header type register is set for function 0 of a PCI device, it is a multi-function device, which contains several (similar or independent) functions on one chip.
If the
window[1c] = type I/O Port, range 16, addr 0x5000-0x8fff, enabled
The first value after the "window" prefix in the square brackets is the offset of the decoding window in config space in hexadecimal. The type of a window is one of "Memory", "Prefetchable Memory", or "I/O Port". The range indicates the binary log of the maximum address the window decodes. The address field indicates the start and end addresses of the decoded range. Finally, the last flag indicates if the window is enabled or disabled.
If the
bar [10] = type Memory, range 32, base 0xda060000, size 131072, enabled
The first value after the "bar" prefix in the square brackets is the offset of the BAR in config space in hexadecimal. The type of a BAR is one of "Memory", "Prefetchable Memory", or "I/O Port". The range indicates the binary log of the maximum address the BAR decodes. The base and size indicate the start and length of the BAR's address window, respectively. Finally, the last flag indicates if the BAR is enabled or disabled.
If the
cap 10[40] = PCI-Express 1 root port
The first value after the "cap" prefix is the capability ID in hexadecimal. The second value in the square brackets is the offset of the capability in config space in hexadecimal. The format of the text after the equals sign is capability-specific.
Each extended capability is enumerated via a line in a similar format:
ecap 0002[100] = VC 1 max VC0
The first value after the "ecap" prefix is the extended capability ID in hexadecimal. The second value in the square brackets is the offset of the extended capability in config space in hexadecimal. The format of the text after the equals sign is capability-specific.
If the
If the
If the
VPD ro PN = '110114640C0 '
The first string after the "VPD" prefix indicates if the keyword is read-only "ro" or read-write "rw". The second string provides the keyword name. The text after the equals sign lists the value of the keyword which is usually an ASCII string.
If the optional
device
argument is given with the
All invocations of
pciconf
except for
In the case of an abridged form, omitted selector components are assumed to be 0.
An optional leading device name followed by @ and an optional final colon
will be ignored; this is so that the first column in the output of
pciconf
With the
The
The
For read, write, and dump operations, the flags
It might be useful to give non-root users access to the
There is currently no way to specify the caching mode for the mapping
established by the
PCICONF (8) | June 14, 2018 |
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